A) Field
The embodiments relate to a semiconductor device with STI and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device with STI having structures of different heights on a plurality of active regions, and a method for manufacturing the semiconductor device of this type. A semiconductor device has typically nonvolatile memory cells with floating gates and MOS transistors of logic circuits.
B) Description of the Related Art
In a semiconductor integrated circuit device (IC), a logic circuit is usually made of a complementary MOS (CMOS) circuit including n-channel MOS (NMOS) transistors and p-channel MOS (PMOS) transistors in order to reduce consumption power. In order to meet the requirements for high integration and high speed of a semiconductor integrated circuit device (IC), transistors as IC constituent elements have been miniaturized. Miniaturization based upon scaling law improves an operation speed of transistors and lowers an operation voltage.
An isolation region made by local oxidation of silicon (LOCOS) produces bird's beak portion which gradually reduces its thickness from a target silicon oxide film thickness, narrows an active region area and constitutes wasteful area, hindering improvement of an integration density. In place of LOCOS, STI (shallow trench isolation) has been used widely.
An isolation region by STI is formed in the following manner. A silicon substrate surface is thermally oxidized to form a buffer silicon oxide film, and a silicon nitride film is deposited on the buffer silicon oxide film by chemical vapor deposition (CVD). A resist pattern having an opening pattern corresponding to the isolation region is formed, and the silicon nitride film and silicon oxide film are etched. By using the patterned silicon nitride film as a mask, the silicon substrate is etched to form an isolation trench. The isolation trench defines active regions. After the surface of the isolation trench is thermally oxidized, the isolation trench is filled with a silicon oxide film by high density plasma (HDP) CVD or the like. The silicon oxide film on the silicon nitride film is removed by chemical mechanical polishing (CMP). The silicon nitride film functions as a CMP stopper. The wafer surface after CMP is in a planarized state. The exposed silicon nitride film is etched and removed with hot phosphoric acid, and the buffer silicon oxide film is etched and removed with dilute hydrofluoric acid to expose the surfaces of active regions.
After the formation of STI, the active region surface is thermally oxidized to form an ion implantation sacrificial silicon oxide film, and ion implantation is performed for well formation, channel stop formation and threshold voltage adjustment suitable for respective transistors. After ion implantation, the sacrificial silicon oxide film is etched and removed. The active region surface is again thermally oxidized to form a gate silicon oxide film. In forming gate silicon oxide films having different thicknesses, some gate silicon oxide films are etched and removed, and new gate silicon oxide films are formed. A gate electrode layer of polysilicon or the like is deposited on the gate silicon oxide films and patterned by etching using a resist mask.
The surface of the STI isolation region becomes higher than the active region surfaces. If over-etch is performed when the butter silicon oxide film is etched, the STI silicon oxide film is also etched so that the STI silicon oxide film is retracted near at the peripheries of the exposed active regions, and a concave portion sinking down from the active region surfaces is formed. As the processes of thermal oxidation and the oxide film etching are repeated, the STI silicon oxide film is further retracted, and the concave portion sinking down from the active region surfaces becomes deeper.
If distribution densities of isolation regions of a wafer are different, dishing occurs in a low density area during CMP. In the area with dishing, an amount of STI protrusion from the substrate surface reduces.
Japanese Patent Laid-open Publication No. 2003-297950 describes that as STI is formed in an integrated circuit device including a DRAM memory cell area and a peripheral circuit area, dishing occurs in the peripheral circuit area due to a different pattern density, forming a height difference between silicon oxide films and that a defect density of gate insulating films in the peripheral circuit area is minimum at an STI height relative to the silicon substrate surface is 20 nm, and a defect density of gate insulating films in the memory cell area is minimum at an STI height of 0 nm. It proposes that after CMP of the STI silicon oxide film, the peripheral circuit area is covered with a mask, and STI in the memory cell area is etched to lower STI in the memory cell area, for example, by 20 nm than the STI height in the peripheral circuit area. With this selective etching, protrusion amount of STI from the active area surface realizes the above-described best STI heights, i.e., about 20 nm in the peripheral circuit area and about 0 nm in the memory cell area.
Japanese Patent Laid-open Publication No. 2006-32700 describes that if there is an STI protrusion difference relative to a silicon substrate surface between a DRAM memory cell area and a peripheral circuit area, a margin of photolithography becomes small. It proposes, after STI is formed, to etch STI in the memory cell area in ion implantation process for each active region by using a mask for ion implantation in the memory cell area, to average the STI protrusion in the whole wafer area. As STI in the memory area is selectively etched by an amount corresponding to a dishing amount in the peripheral circuit area, the STI protrusion can be made uniform. Although the protrusion amount is reduced by etching STI in the memory cell area, similar to Japanese Patent Laid-open Publication No. 2003-297950, the object, etching timing and etching amount are different.
These proposals pertain to adjustment of an STI protrusion amount when DRAM memory cells are integrated with the peripheral circuit area.
Logic semiconductor devices embedded nonvolatile semiconductor memories constitute product fields such as a complex programmable logic array (CPLD) and a field programmable gate array (FPGA), and form a large market because of the feature of “programmable”. A typical example of a rewritable nonvolatile semiconductor memory is a flash memory having a gate electrode structure including a lamination of a tunneling insulating film, a floating gate electrode, an inter-gate insulating film and a control gate, substituting an insulated gate electrode structure made of a gate insulating film and a gate electrode on the gate insulating film of an NMOS transistor. An operation voltage of a flash memory is high because charges in the floating gate electrode are written/erased and the channel is controlled via the floating gate electrode by a voltage at the control electrode.
In a logic semiconductor device embedded nonvolatile memory, in addition to flash memory cells, high voltage transistors for flash memory control and low voltage transistors for a high performance logic circuit are integrated on the same semiconductor chip. In order to form a transistor having a low threshold voltage and a transistor having a high threshold voltage, it is necessary to change the conditions of threshold voltage adjustment ion implantation. As ion implantation is performed independently for an NMOS area and a PMOS area, four masks and eight ion implantation processes are required for transistors of four types including a high voltage operation CMOS and a low voltage operation CMOS.
International Publication WO2004/093192, which is incorporated herein by reference, discloses a process of forming transistors of eleven types including in addition to a flash memory, NMOS transistors and PMOS transistors operating at a high voltage and a low voltage and having a high threshold voltage and a low threshold voltage and an NMOS transistor and a PMOS transistor operating at a middle voltage for externally input signals. It proposes an ion implantation method for NMOS (or PMOS) transistors of three types which method uses three masks and four ion implantation processes.
In transistor areas at different operation voltages, a plurality of types of gate insulating films having difference thicknesses are formed. In order to form a thick gate insulating film and a thin gate insulating film, for example, thick gate silicon oxide films are formed first in the whole active region surfaces, and thick gate silicon oxide films are selectively removed from the area where thin gate silicon oxide films are to be formed. Thereafter, thin gate silicon oxide films are formed. In order to form gate silicon oxide films having three different thicknesses, a process of etching a gate silicon oxide film and a succeeding process of forming a gate silicon oxide film are required to be executed twice. In etching the silicon oxide film, an over-etch is performed and the silicon oxide film in the isolation area near the active region is also etched. As the silicon oxide film is etched repetitively, the isolation region has a concave portion not negligible at the boundary of the active region.
The gate electrode of a flash memory has a structure that a control gate is laminated above a floating gate via an ONO film (silicon oxide film/silicon nitride film/silicon oxide film). The floating gate is a gate electrode which takes an electrically floating state, usually made of polysilicon, and patterned by two etching processes. It is not always easy to etch the polysilicon layer whose surface is covered with the ONO film. This difficulty increases if the peripheral area of the active region is surrounded by STI having a concave portion or a protrusion portion and etching is performed at a sloped surface. Since the control gate of a flash memory is formed above the floating gate, the surface of the control gate becomes higher than the surface of the gate electrode of a MOS transistor of a peripheral circuit.
A semiconductor device integrating a flash memory area and a logic circuit area may have a problem different from the problem of a semiconductor device integrating a DRAM memory cell area and a logic circuit area.
Patent Documents:
    1) Japanese Patent Laid-open Publication No. 2003-297950    2) Japanese Patent Laid-open Publication No. 2006-032700    3) International Publication no. WO 2004/093192